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MC14LC5540 motorola 1 technical summary
this technical summary provides a brief description of the MC14LC5540 adpcm codec. a complete data book for the MC14LC5540 is available and can be ordered from your local motorola sales office. the data book number is mc145540/d. the MC14LC5540 adpcm codec is a single chip implementation of a pcm codecfilter and an adpcm encoder/decoder, and therefore provides an efficient solution for applications requiring the digitization and compression of voiceband signals. this device is designed to operate over a wide voltage range, 2.7 to 5.25 v and, as such, is ideal for battery powered as well as ac powered applications. the MC14LC5540 adpcm codec also includes a serial control port and internal control and status registers that permit a microcom- puter to exercise many builtin features. the adpcm codec is designed to meet the 32 kbps adpcm conformance requirements of ccitt recommendation g.7211988 and ansi t1.301. it also meets ansi t1.303 and ccitt recommendation g.7231988 for 24 kbps adpcm operation, and the 16 kbps adpcm standard, ccitt recommen- dation g.726. this device also meets the pcm conformance specification of the ccitt g.714 recommendation. ? single 2.7 to 5.25 v power supply ? typical 2.7 v power dissipation of 43 mw, powerdown of 15 m w ? differential analog circuit design for lowest noise ? complete mulaw and alaw companding pcm codecfilter ? adpcm transcoder for 64, 32, 24, and 16 kbps data rates ? universal programmable dual tone generator ? programmable transmit gain, receive gain, and sidetone gain ? low noise, high gain, three terminal input operational amplifier for microphone interface ? pushpull, 300 w power drivers with external gain adjust for receiver interface ? pushpull, 300 w auxiliary output drivers for ringer interface ? voltage regulated charge pump to power the analog circuitry in low voltage applications ? receive noise burst detect algorithm ? order complete document as mc145540/d ? device supported by mc145537evk adpcm codec evaluation kit this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. order this document by MC14LC5540ts/d
semiconductor technical data
p suffix plastic dip case 710 dw suffix sog package case 751f ordering information MC14LC5540p plastic dip MC14LC5540dw sog package MC14LC5540fu tqfp 28 1 28 1 32 1 fu suffix tqfp case 873a ? motorola, inc. 1997 rev 2 6/97 tn97060200
MC14LC5540 motorola 2 pin assignment 19 18 17 16 15 28 27 26 25 24 23 22 21 20 tg ti ti + v ag ro axo axo + v dsp v ext pi po po + pdi /reset scpen v dd fsr bclkr dr c1 + v ss spc dt bclkt fst scp rx scp tx scpclk c1 10 11 12 13 14 1 2 3 4 5 6 7 8 9 ? 28lead pdip, sog ro axo axo+ nc v dsp nc v ext pi po po+ pdi/reset scpen scp clk fst v ti+ ti tg v 32 31 30 29 28 27 26 25 4 3 2 6 5 8 7 1 17 18 20 21 19 22 23 24 9 10111213141516 v ss c1+ nc c1 nc dt spc bclkt scp rx scp tx fsr dr bclkr 32lead tqfp dd ag pdi /reset v dsp axo dac sidetone gain adc scp tx trim gain and filter + pi po po + 1 ti + trim gain and filter scp rx scpclk scpen ro + dsp adpcm transcoder, receive gain and dual tone generator chargepump codecfilter sequence/ control c1 c1 + v ss v ag v dd v ext ti tg axo + spc fsr bclkr dr dt fst bclkt s block diagram
MC14LC5540 motorola 3 pin descriptions power supply pins v ss negative power supply (pdip, sogepin 22; tqfpepin 21) this is the most negative power supply and is typically connected to 0 v. v ext external power supply input (pdip, sogepin 9; tqfpepin 7) this power supply input pin must be between 2.70 and 5.25 v. internally, it is connected to the input of the v dsp voltage regulator, the 5 v regulated charge pump, and all digital i/o including the serial control port and the adpcm serial data port. this pin is also connected to the analog out- put drivers (po+, po, axo+, and axo). this pin should be decoupled to v ss with a 0.1 m f ceramic capacitor. this pin is internally connected to the v dd and v dsp pins when the device is powered down. v dsp digital signal processor power supply output (pdip, sogepin 8; tqfpepin 5) this pin is connected to the output of the onchip v dsp voltage regulator which supplies the positive voltage to the dsp circuitry and to the other digital blocks of the adpcm codec. this pin should be decoupled to v ss with a 0.1 m f ceramic capacitor. this pin cannot be used for powering external loads. this pin is internally connected to the v ext pin during powerdown to retain memory. v dd positive power supply input/output (pdip, sog, tqfpepin 28) this is the positive output of the onchip voltage regulated charge pump and the positive power supply input to the ana- log sections of the device. depending on the supply voltage available, this pin can function in one of two different oper- ating modes: 1. when v ext is supplied from a regulated 5 v ( 5%) power supply, v dd is an input and should be externally connected to v ext . charge pump capacitor c1 should not be used and the charge pump should be disabled in br0 (b2). in this case v ext and v dd can share the same 0.1 m f ceramic decoupling capacitor to v ss . 2. when v ext is supplied from 2.70 to 5.25 v, such as battery powered applications, the charge pump should be used. in this case, v dd is the output of the onchip voltage regulated charge pump and must not be con- nected to v ext . v dd should be decoupled to v ss with a 1.0 m f ceramic capacitor. this pin cannot be used for powering external loads in this operating mode. this pin is internally connected to the v ext pin when the charge pump is turned off or the device is powered down. v ag analog ground output (pdip, sogepin 4; tqfpepin 32) this output pin provides a midsupply analog ground reg- ulated to 2.4 v. all analog signal processing within this device is referenced to this pin. this pin should be decoupled to v ss with a 0.01 m f ceramic capacitor. if the audio signals to be processed are referenced to v ss , then special precautions must be utilized to avoid noise between v ss and the v ag pin. refer to the applications information in this document for more information. the v ag pin becomes high impedance when in analog powerdown mode. c1, c1+ charge pump capacitor pins (pdip, sog, tqfpepins 23 and 24) these are the capacitor connections to the internal voltage regulated charge pump that generates the v dd supply volt- age. a 0.1 m f capacitor should be placed between these pins. note that if an external v dd is supplied, this capacitor should not be in the circuit. analog interface pins tg transmit gain (pdip, sogepin 1; tqfpepin 29) this is the output of the transmit gain setting operational amplifier and the input to the transmit bandpass filter. this op amp is capable of driving a 2 k w load to the v ag pin. when ti and ti+ are connected to v dd , the tg op amp is powered down and the tg pin becomes a highimpedance input to the transmit filter. all signals at this pin are refer- enced to the v ag pin. this pin is high impedance when the device is in the analog powerdown mode. this op amp is powered by the v dd pin. ti transmit analog input (inverting) (pdip, sogepin 2; tqfpepin 30) this is the inverting input of the transmit gain setting op- erational amplifier. gain setting resistors are usually con- nected from this pin to tg and from this pin to the analog signal source. the common mode range of the ti+ and ti pins is from 1.0 v, to v dd 2 v. connecting this pin and ti + to v dd will place this amplifier's output (tg) in a highimped- ance state, thus allowing the tg pin to serve as a highim- pedance input to the transmit filter. ti+ transmit analog input (noninverting) (pdip, sogepin 3; tqfpepin 31) this is the noninverting input of the transmit input gain setting operational amplifier. this pin accommodates a differ- ential to singleended circuit for the input gain setting op amp. this allows input signals that are referenced to the v ss pin to be level shifted to the v ag pin with minimum noise. this pin may be connected to the v ag pin for an inverting amplifier configuration if the input signal is already refer- enced to the v ag pin. the common mode range of the ti+ and ti pins is from 1.0 v to v dd 2 v. connecting this pin and ti to v dd will place this amplifier's output (tg) in a
MC14LC5540 motorola 4 highimpedance state, thus allowing the tg pin to serve as a highimpedance input to the transmit filter. ro receive analog output (pdip, sogepin 5; tqfpepin 1) this is the noninverting output of the receive smoothing filter from the digitaltoanalog converter. this output is capable of driving a 2 k w load to 1.575 v peak referenced to the v ag pin. this pin may be dc referenced to either the v ag pin or a voltage of half of v ext by br2 (b7). this pin is high impedance when the device is in the analog powerdown mode. this pin is high impedance except when it is enabled for analog signal output. axo auxiliary audio power output (inverting) (pdip, sogepin 6; tqfpepin 3) this is the inverting output of the auxiliary power output drivers. the auxiliary power driver is capable of differentially driving a 300 w load. this power amplifier is powered from v ext and its output can swing to within 0.5 v of v ss and v ext . this pin may be dc referenced to either the v ag pin or a voltage of half of v ext by br2 (b7). this pin is high imped- ance in power down. this pin is high impedance except when it is enabled for analog signal output. axo+ auxiliary audio power output (noninverting) (pdip, sogepin 7; tqfpepin 4) this is the noninverting output of the auxiliary power out- put drivers. the auxiliary power driver is capable of differen- tially driving a 300 w load. this power amplifier is powered from v ext and its output can swing to within 0.5 v of v ss and v ext . this pin may be dc referenced to either the v ag pin or a voltage of half of v ext by br2 (b7). this pin is high imped- ance in power down. this pin is high impedance except when it is enabled for analog signal output. pi power amplifier input (pdip, sogepin 10; tqfpepin 8) this is the inverting input to the po amplifier. the non inverting input to the po amplifier may be dc referenced to either the v ag pin or a voltage of half of v ext by br2 (b7). the pi and po pins are used with external resistors in an inverting op amp gain circuit to set the gain of the po + and po pushpull power amplifier outputs. connecting pi to v dd will power down these amplifiers and the po+ and po outputs will be high impedance. po power amplifier output (inverting) (pdip, sogepin 11; tqfpepin 9) this is the inverting power amplifier output that is used to provide a feedback signal to the pi pin to set the gain of the pushpull power amplifier outputs. this power amplifier is powered from v ext and its output can swing to within 0.5 v of v ss and v ext . this should be noted when setting the gain of this amplifier. this pin is capable of driving a 300 w load to po+ independent of supply voltage. the po+ and po out- puts are differential (pushpull) and capable of driving a 300 w load to 3.15 v peak, which is 6.3 v peaktopeak when a nominal 5 v power supply is used for v ext . the bias voltage and signal reference for this pin may be dc refer- enced to either the v ag pin or a voltage of half of v ext by br2 (b7). low impedance loads must be between po+ and po. this pin is high impedance when the device is in the analog powerdown mode. this pin is high impedance ex- cept when it is enabled for analog signal output. po+ power amplifier output (noninverting) (pdip, sogepin 12; tqfpepin 10) this is the noninverting power amplifier output that is an inverted version of the signal at po. this power amplifier is powered from v ext and its output can swing to within 0.5 v of v ss and v ext . this pin is capable of driving a 300 w load to po. this pin may be dc referenced to either the v ag pin or a voltage of half of v ext by br2 (b7). this pin is high impedance when the device is in the analog powerdown mode. see pi and po for more information. this pin is high impedance except when it is enabled for analog signal out- put. adpcm/pcm serial interface pins fst frame sync, transmit (pdip, sogepin 18; tqfpepin 16) when used in the long frame sync or short frame sync mode, this pin accepts an 8 khz clock that synchronizes the output of the serial adpcm data at the dt pin. bclkt bit clock, transmit (pdip, sogepin 19; tqfpepin 17) when used in the long frame sync or short frame sync mode, this pin accepts any bit clock frequency from 64 to 5120 khz. dt data, transmit (pdip, sogepin 20; tqfpepin 18) this pin is controlled by fst and bclkt and is high im- pedance except when outputting data. spc signal processor clock (pdip, sogepin 21; tqfpepin 19) this input requires a 20.48 to 24.32 mhz clock signal that is used as the dsp engine master clock. internally the device divides down this clock to generate the 256 khz clock re- quired by the pcm codec. the spc clock should be a multi- ple of 256 khz. (this clock may be optionally specified for higher frequencies; contact the factory for more information.) dr data, receive (pdip, sog, tqfpepin 25) adpcm data to be decoded are applied to this input, which operates synchronously with fsr and bclkr to enter the data in a serial format.
MC14LC5540 motorola 5 bclkr bit clock, receive (pdip, sog, tqfpepin 26) when used in the long frame sync or short frame sync mode, this pin accepts any bit clock frequency from 64 to 5120 khz. this pin may be used for applying an external 256 khz clock for sequencing the analog signal processing functions of this device. this is selected by the scp port at br0 (b7). fsr frame sync, receive (pdip, sog, tqfpepin 27) when used in the long frame sync or short frame sync mode, this pin accepts an 8 khz clock that synchronizes the input of the serial adpcm data at the dr pin. fsr can oper- ate asynchronous to fst in the long frame sync or short frame sync mode. serial control port interface pins pdi /reset powerdown input/reset (pdip, sogepin 13; tqfpepin 11) a logic 0 applied to this input forces the device into a low power dissipation mode. a rising edge on this pin causes power to be restored and the adpcm reset state (specified in the standards) to be forced. scpen serial control port enable input (pdip, sogepin 14; tqfpepin 12) this pin, when held low, selects the serial control port (scp) for the transfer of control and status information into and out of the MC14LC5540 adpcm codec. this pin should be held low for a total of 16 periods of the scpclk signal in order for information to be transferred into or out of the MC14LC5540 adpcm codec. the timing relationship be- tween scpen and scpclk is shown in figures 6 through 9. scpclk serial control port clock input (pdip, sogepin 15; tqfpepin 13) this input to the device is used for controlling the rate of transfer of data into and out of the scp interface. data are clocked into the MC14LC5540 adpcm codec from scp rx on rising edges of scpclk. data are shifted out of the de- vice on scp tx on falling edges of scpclk. scpclk can be any frequency from 0 to 4.096 mhz. an scp transaction takes place when scpen is brought low. note that scpclk is ignored when scpen is high ( i.e., it may be continuous or it can operate in a burst mode). scp tx serial control port transmit output (pdip, sogepin 16; tqfpepin 14) scp tx is used to output control and status information from the MC14LC5540 adpcm codec. data are shifted out of scp tx on the falling edges of scpclk, most significant bit first. scp rx serial control port receive input (pdip, sogepin 17; tqfpepin 15) scp rx is used to input control and status information to the MC14LC5540 adpcm codec. data are shifted into the device on rising edges of scpclk. scp rx is ignored when data are being shifted out of scp tx or when scpen is high.
MC14LC5540 motorola 6 adpcm/pcm serial interface timing diagrams don't care dr 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 dt bclkt (bclkr) fst (fsr) don't care figure 1. long frame sync (64 kbps pcm data timing) dr 4 3 2 1 4 3 2 1 dt bclkt (bclkr) fst (fsr) don't care don't care figure 2. long frame sync (32 kbps adpcm data timing) dr 3 2 1 3 2 1 dt bclkt (bclkr) fst (fsr) don't care don't care figure 3. long frame sync (24 kbps adpcm data timing) dr 2 1 2 1 dt bclkt (bclkr) fst (fsr) don't care don't care figure 4. long frame sync (16 kbps adpcm data timing)
MC14LC5540 motorola 7 dr 4 3 2 1 4 3 2 1 dt bclkt (bclkr) fst (fsr) don't care don't care figure 5. short frame sync (32 kbps adpcm data timing) ??? ??? ??? ??? ????? ????? a3 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 r/w scp tx scp rx scpclk scpen don't care ??? ??? ??? ??? high impedance ????? ????? don't care figure 6. scp byte register write operation using double 8bit transfer ??????????????? ??????????????? ??? ??? ??? ???? ???? ???? ??? ??? ??? ??? ??? a3 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 r/w scp tx scp rx scpclk scpen don't care don't care high impedance figure 7. scp byte register read operation using double 8bit transfer ?????? ?????? ?????? ?????? ??? ??? ??? ??? a3 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 don't care don't care scp tx scp rx scpclk scpen r/w high impedance figure 8. scp byte register write operation using single 16bit transfer
MC14LC5540 motorola 8 ???????????????? ???????????????? ?????? ?????? ??? ??? ??? ??? a3 d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 scp tx scp rx scpclk scpen don't care r/w high impedance don't care figure 9. scp byte register read operation using single 16bit transfer serial control port (scp) interface the MC14LC5540 is equipped with an industry standard serial control port (scp) interface. the scp is used by an external controller, such as an m68hc05 family micro- controller, to communicate with the MC14LC5540 adpcm codec. the scp is a fullduplex, fourwire interface used to pass control and status information to and from the adpcm codec. the scp interface consists of a transmit output, a receive input, a data clock, and an enable signal. these device pins are known as scp tx, scp rx, scpclk, and scpen , respectively. the scpclk determines the rate of exchange of data in both the transmit and receive directions, and the scpen signal governs when this exchange is to take place. the operation and configuration of the adpcm codec is controlled by setting the state of the control and status regis- ters within the MC14LC5540 and then monitoring these con- trol and status registers. the control and status registers reside in sixteen 8bit wide byte registers, br0 br15. a complete register map can be found in the serial control port registers section. byte register operations the sixteen byte registers are addressed by addressing a fourbit byte register address (a3:a0) as shown in figures 6 and 7. a second 8bit operation transfers the data word (d7:d0). alternatively, these registers can be accessed with a single 16bit operation as shown in figures 8 and 9. adpcm codec device description the MC14LC5540 is a single channel mulaw or alaw companding pcm codecfilter with an adpcm encoder/de- coder operating on a single voltage power supply from 2.7 to 5.25 v. the MC14LC5540 adpcm codec is a complete solution for digitizing and reconstructing voice in compliance with ccitt g.714, g.7211988, g.7231988, g.726, and ansi t1.301 and t1.303 for 64, 32, 24, and 16 kbps. this device satisfies the need for highquality, lowpower, low data rate voice transmission, and storage applications and is offered in three plastic packages: the 28pin dip and 28pin soic di- rectly replace the mc145540, and the 32pin tqfp (thin quad flat package) is a new addition. referring to figure 10, the main functional blocks of the MC14LC5540 are the switched capacitor technology pcm codecfilter, the dsp based adpcm encoder/decoder, and the voltage regulated charge pump. as an introduction to the functionality of the adpcm codec, a basic description of these functional blocks follows. pcm codecfilter block description a pcm codecfilter is a device used for digitizing and re- constructing the human voice. these devices were devel- oped primarily for the telephone network to facilitate voice switching and transmission. once the voice is digitized, it may be switched by digital switching methods or transmitted long distance (t1, microwave, fiber optics, satellites, etc.) without degradation. the name codec is an acronym from acodero for the analogtodigital converter (adc) used to digitize voice, and adecodero for the digitaltoanalog con- verter (dac) used for reconstructing voice. a codec is a single device that does both the adc and dac conversions. to digitize voice intelligibly requires a signal to distortion of about 30 db for a dynamic range of about 40 db. this may be accomplished with a linear 13bit adc and dac, but will far exceed the required signal to distortion at amplitudes greater than 40 db below the peak amplitude. this excess perfor- mance is at the expense of bits of data per sample. two methods of data reduction are implemented by compressing the 13bit linear scheme to companded 8bit schemes. these companding schemes follow a segmented or apiece- wiselinearo curve formatted as sign bit, three chord bits, and four step bits. for a given chord, all 16 of the steps have the same voltage weighting. as the voltage of the analog input increases, the four step bits increment and carry to the three chord bits, which increment. when the chord bits increment, the step bits double their voltage weighting. this results in an effective resolution of six bits (sign + chord + four step bits) across a 42 db dynamic range (seven chords above 0, by 6 db per chord). there are two companding schemes used: mu255 law specifically in north america and alaw specifically in europe. these companding schemes are accepted world wide.
MC14LC5540 motorola 9 serial control port sequence and control output shift register input shift register fsr length circuitry fst length circuitry adpcm serial data port adpcm decoder noiseburst detect circuit adpcm encoder companded to linear universal dual tone generator linear to companded receive digital gain digital signal processor analog interface and codecfilter power supply management subsystem dac s sidetone gain adc trim gain and filter trim gain and filter 2.4 v reference 1 + + 2.3 v regulator for digital signal processor 5 v regulated charge pump for codecfilter analog processing po + po pi ro axo axo + tg ti ti + dr fsr bclkr bclkt fst dt spc pdi / reset scp tx scp rx scpclk scpen v c1 c1 + dsp v ext v ss v dd v ag figure 10. adpcm codec block diagram
MC14LC5540 motorola 10 in a sampling environment, nyquist theory says that to properly sample a continuous signal, it must be sampled at a frequency higher than twice the signal's highest frequency component. voice contains spectral energy above 3 khz, but its absence is not detrimental to intelligibility. to reduce the digital data rate, which is proportional to the sampling rate, a sample rate of 8 khz was adopted, consistent with a band- width of 3 khz. this sampling requires a lowpass filter to limit the high frequency energy above 3 khz from distorting the inband signal. the telephone line is also subject to 50/60 hz power line coupling, which must be attenuated from the signal by a highpass filter before the analogto digital converter. the digitaltoanalog conversion process reconstructs a staircase version of the desired inband signal which has spectral images of the inband signal modulated about the sample frequency and its harmonics. these spectral images are called aliasing components which need to be attenuated to obtain the desired signal. the lowpass filter used to at- tenuate these aliasing components is typically called a re- construction or smoothing filter. the MC14LC5540 adpcm codec incorporates this codec function as one of its main functional blocks. adpcm transcoder block description an adaptive differential pcm (adpcm) transcoder is used to reduce the data rate required to transmit a pcm encoded voice signal while maintaining the voice fidelity and intel- ligibility of the pcm signal. the adpcm transcoder is used on both mulaw and alaw 64 kbps data streams which represent either voice or voice band data signals that have been digitized by a pcm codecfilter. the pcm to adpcm encoder section of this transcoder has a type of linear predicting digital filter which is trying to predict the next pcm sample based on the previous history of the pcm samples. the adpcm to pcm decoder section implements an identical linear predicting digital filter. the error or difference between the predicted and the true pcm input value is the information that is sent from the en- coder to the decoder as an adpcm word. the characteris- tics of this adpcm word include the number of quantized steps (this determines the number of bits per adpcm word) and the actual meaning of this word is a function of the pre- dictor's output value, the error signal and the statistics of the history of pcm words. the term aadaptiveo applies to the transfer function of the filter that generates the adpcm word which adapts to the statistics of the signals presented to it. this means that an adpcm word a3o does not have the same absolute error voltage weighting for the analog signal when the channel is quiet as it does when the channel is pro- cessing a speech signal. the adpcm to pcm decoder sec- tion has a reciprocating filter function which interprets the adpcm word for proper reconstruction of the pcm sample. the adaptive characteristics of the adpcm algorithm make it difficult to analyze and quantify the performance of the adpcm code sequence. the 32 kbps algorithm was op- timized for both voice and moderate speed modems ( 4800 baud). this optimization includes that the algorithm supports the voice frequency band of 300 3400 hz with minimal degradation for signaltodistortion, gainversus level, idle channel noise, and other analog transmission per- formance. this algorithm has also been subjected to audibility testing with many languages for mean opinion score (mos) ratings and performed well when compared to 64 kbps pcm. the standards committees have specified multiple 16000 word test vectors for the encoder and for the decoder to verify compliance. to run these test vectors, the device must be initialized to the reference state by resetting the device. in contrast to 64 kbps pcm, the adpcm words appear as random bit activity on an oscilloscope display whether the audio channel is processing speech or a typical pcm idle channel with nominal bit activity. the adpcm algorithm does not support dc signals with the exception of digital quiet, which will result in all ones in the adpcm channel. all digital processing is performed on 13bit linearizations of the 8bit pcm companded words, whether the words are mulaw or alaw. this allows an adpcm channel to be intelligibly de- coded into a mulaw pcm sequence or an alaw pcm se- quence irrespective of whether it was originally digitized as mulaw or alaw. there will be additional quantizing degra- dation if the companding scheme is changed because the adpcm algorithm is trying to reconstruct the original 13bit linear codes, which included companding quantization. charge pump the charge pump is the functional block that allows the analog signal processing circuitry of the MC14LC5540 to op- erate with a power supply voltage as low as 2.7 v. this ana- log signal processing circuitry includes the pcm codecfilter function, the transmit trim gain, the receive trim gain, the sidetone gain control, and the transmit input opera- tional amplifier. this circuitry does not dissipate much current but it does require a nominal voltage of 5 v for the v dd power supply. the charge pump block is a regulated voltage doubler which takes twice the current it supplies from the voltage ap- plied to the v ext power supply pin which may range from 2.7 to 5.25 v and generates the required 5 v v dd supply. the charge pump block receives as inputs the v ext supply volt- age, the same 256 khz clock that sequences the analog sig- nal processing circuitry, and the charge pump enable signal from the scp block. it also makes use of the capacitor con- nected to the c1+ and c1 pins and the decoupling capacitor connected to the v dd pin. functional description power supply configuration analog signal processing power supply all analog signal processing is powered by the v dd pin at 5 v. this voltage may be applied directly to the v dd pin or 5 v may be obtained by the onchip 5 v regulated charge pump which is powered from the v ext pin. the v ext pin is the main positive power supply pin for this device. for applications that are not 5 v regulated, the onchip 5 v regulated charge pump may be turned on and c1 will be re- quired. v dd will require a 1.0 m f decoupling capacitor to filter the voltage spikes of the charge pump. this allows the v ext power supply to be from 2.7 to 5.25 v. this mode of opera- tion is intended for hand held applications where three nicad cells or three dry cells would be the power supply. the onchip 5 v regulated charge pump is a single stage charge pump that effectively series regulates the amount of voltage it generates and internally applies this regulated voltage to the v dd pin. this 5 v voltage is developed by
MC14LC5540 motorola 11 connecting the external 0.1 m f capacitor (c1) between the v ext power supply pin and the power supply ground pin, v ss . this puts a charge of as much as 2.7 v on c1. the charge pump circuitry then connects the negative lead of c1 to the v ext , pin which sums the voltage of c1 with the volt- age at v ext for a minimum potential voltage of 5.4 v. the charge voltage on c1 is regulated such that the summing of voltages is regulated to 5 v. this limits all of the voltages on the device to safe levels for this ic fabrication technology. this charge pumped voltage is then stored on the 1.0 m f ca- pacitor connected at v dd and v ss , which filters and serves as a reservoir for power. the clock period for this charge pump is the same 256 khz as the analog sequencing clock, minimizing noise problems. for applications with a regulated 5 v ( 5%) power supply, the v dd pin and the v ext pin are connected to the 5 v power supply. these pins may share one decoupling capacitor in this configuration as a function of external noise on the power supply. the onchip, 5 v regulated charge pump should be turned off via the scp port at register 0. the external capacitor (c1) should not be populated for these applications. digital signal processing power supply this device has an onchip series regulator which limits the voltage of the digital signal processing (dsp) circuitry to about 2.3 v. this reduces the maximum power dissipation of this circuitry. from the v ext power supply pin, the dsp cir- cuitry appears as a constant current load instead of a resis- tive (cv 2 /2) load for a constant clock frequency. this series regulator is designed to have a low dropout voltage, which allows the dsp circuitry to work when the v ext voltage is as low as 2.7 v. the output of this regulator is brought out to the v dsp pin for a 0.1 m f decoupling capacitor. this regulator is not designed to power any loads external to the device. analog interface and signal path transmit analog the transmit analog portion of this device includes a low noise, three terminal operational amplifier capable of driving a 2 k w load. this op amp has inputs of ti+ and ti and its output is tg. this op amp is intended to be configured in an inverting gain circuit. the analog signal may be applied di- rectly to the tg pin if this transmit op amp is independently powered down. powerdown may be achieved by connect- ing both the ti+ and ti inputs to the v dd pin. the tg pin becomes high impedance when the transmit op amp is pow- ered down. the tg pin is internally connected to a time con- tinuous threepole antialiasing prefilter. this prefilter incorporates a twopole butterworth active lowpass filter, followed by a single passive pole. this prefilter is followed by a singleended to differential converter that is clocked at 512 khz. all subsequent analog processing utilizes fully dif- ferential circuitry. the output of the differential converter is followed by the transmit trim gain stage. this stage is in- tended to compensate for gain tolerances of external compo- nents such as microphones. the amount of gain control is 07 db in 1 db steps. this stage only accommodates posi- tive gain because the maximum signal levels of the output of the input op amp are the same as the transmit filter and adc, which should nominally be next to the clip levels of this de- vice's circuitry. any requirement for attenuation of the output of the input op amp would mean that it is being overdriven. the gain is programmed via the scp port in br1 (b2:b0). the next section is a fullydifferential, 5pole switchedca- pacitor lowpass filter with a 3.4 khz frequency cutoff. after this filter is a 3pole switchedcapacitor highpass filter hav- ing a cutoff frequency of about 200 hz. this highpass stage has a transmission zero at dc that eliminates any dc coming from the analog input or from accumulated op amp offsets in the preceding filter stages. (this highpass filter may be re- moved from the signal path under control of the scp port br8 (b4).) the last stage of the highpass filter is an auto- zeroed sample and hold amplifier. one bandgap voltage reference generator and digitalto analog converter (dac) are shared by the transmit and receive sections. the autozeroed, switchedcapacitor band- gap reference generates precise positive and negative refer- ence voltages that are virtually independent of temperature and power supply voltage. a binaryweighted capacitor array (cdac) forms the chords of the companding structure, while a resistor string (rdac) implements the linear steps within each chord. the encode process uses the dac, the voltage reference, and a framebyframe autozeroed comparator to implement a successiveapproximation ana- logtodigital conversion (adc) algorithm. all of the analog circuitry involved in the data conversion (the voltage refer- ence, rdac, cdac, and comparator) are implemented with a differential architecture. the nonlinear companded mulaw transfer curve of the adc may be changed to 8bit linear by br8 (b5). the input to the adc is normally connected to the output of the transmit filter section, but may be switched to measure the voltage at the v ext pin for battery voltage monitoring. this is selected by the i/o mode in br0 (b4:b3). in this mode, the adc is programmed to output a linear 8bit pcm word for the voltage at v ext which is intended to be read in br9 (b7:b0). the data format for the adc output is a adon't careo for the sign bit and seven magnitude bits. the scaling for the adc is for 6.3 v at v ext equals full scale (bin x111 1111). the adpcm algorithm does not support dc signals. transmit digital the digital signal processor (dsp) section of this device is a custom designed, interrupt driven, microcoded machine optimized for implementing the adpcm algorithms. in the fullduplex speech mode, the dsp services one encode in- terrupt and one decode interrupt per frame (125 m s). the en- code algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps adpcm, or 64 kbps pcm) is determined by the length of the transmit output enable at the fst pin. the length of the fst enable measured in transmit data clock (bclkt) cycles tells the de- vice which encoding rate to use. this enable length informa- tion is used by the encoder each frame. the transmit adpcm word corresponding to this request will be computed during the next frame and will be available a total of two frames after being requested. this transmit enable length in- formation can be delayed by the device an additional four frames corresponding to a total of six frames. these six frames of delay allow the device to be clocked with the same clocks for both transmit (encode) and receive (decode), and to be frame aligned for applications that require every sixth frame signaling. it is important to note that the enable length information is delayed and not the actual adpcm (pcm) sample word. the amount of delay for the fst enable length
MC14LC5540 motorola 12 is controlled in br7 (b5). if the fst enable goes low before the falling edge of bclkt during the last bit of the adpcm word, the digital data output circuitry counts bclkt cycles to keep the data output (dt pin) low impedance for the duration of the adpcm data word (2, 3, 4, or 8 bclkt cycles) minus one half of a bclkt cycle. receive digital the receive digital section of this device accepts serial adpcm (pcm) words at the dr pin under the control of the bclkr and fsr pins. the fsr enable duration, measured in bclkr cycles, tells the device which decode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps adpcm, or 64 kbps pcm) the dsp machine should use for the word that is being re- ceived at the dr pin. this algorithm may be changed on a frame by frame basis. the dsp machine receives an interrupt when an adpcm word has been received and is waiting to be decoded into a pcm word. the dsp machine performs a decode and an encode every frame when the device is operating in its full duplex conversation mode. the dsp machine decodes the adpcm word according to ccitt g.726 for 32 kbps, 24 kbps, and 16 kbps. this decoding includes the correction for the ccitt/ansi sync function, except when the receive digital gain is used. the receive digital gain is anticipated to be user adjustable gain control in handset applications where as much as 12 db of gain or more than 12 db of atten- uation may be desirable. the receive digital gain is a linear multiply performed on the 13bit linear data before it is con- verted to mulaw or alaw, and is programmed via the scp port in br3 (b7:b0). the decoded pcm word may be read via the scp port in br10 (b7:b0). receive analog signal processing the receive analog signal processing section includes the dac described above, a sample and hold amplifier, a trim gain stage, a 5pole, 3400 hz switched capacitor lowpass filter with sinx/x correction, and a 2pole active smoothing filter to reduce the spectral components of the switched ca- pacitor filter. (the receive lowpass smoothing filter may be removed from the signal path for the additional spectral com- ponents for applications using the onchip tone generator function described below. this lowpass filter performs the sinx/x compensation. the receive filter is removed from the circuit via the scp in br2 (b4).) the input to the smoothing filter is the output to the receive trim gain stage. this stage is intended to compensate for gain tolerances of external com- ponents such as handset receivers. this stage is capable of 0 to 7 db of attenuation in 1db steps. this stage only ac- commodates attenuation because the nominal signal levels of the dac should be next to the clip levels of this device's circuitry and any positive gain would overdrive the outputs. the gain is programmed via the scp port in br2 (b2:b0).the output of the 2pole active smoothing filter is buffered by an amplifier which is output at the ro pin. this output is capable of driving a 2 k w load to the v ag pin. receive analog output drivers and power supply the high current analog output circuitry (po+, po, pi, axo+, axo) is powered by the v ext power supply pin. due to the wide range of v ext operating voltages for this device, this circuitry and the ro pin have a programmable reference point of either v ag (2.4 v) or v ext /2. in applications where this device is powered with 5 v, it is recommended that the dc reference for this circuitry be programmed to v ag . this allows maximum output signals for driving high power tele- phone line transformer interfaces and loud speaker/ringers. for applications that are battery powered, v ag pin will still be 2.4 v, but the receive analog output circuitry will be powered from as low as 2.7 v. to optimize the output power, this cir- cuitry should be referenced to one half of the battery voltage, v ext /2. the ro pin is powered by the v dd pin, but its dc reference point is programmed the same as the high current analog output circuitry. this device has two pairs of power amplifiers that are con- nected in a pushpull configuration. these pushpull power driver pairs have similar drive capabilities, but have different circuit configurations and different intended uses. the po+ and po power drivers are intended to accommodate large gain ranges with precise adjustment by two external resistors for applications such as driving a telephone line or a handset receiver. the pi pin is the inverting input to the po power amplifier. the noninverting input is internally tied to the same reference as the ro output. this allows this amplifier to be used in an inverting gain circuit with two external resis- tors. the po+ amplifier has a gain of 1, and is internally connected to the po output. this complete power amplifier circuit is a differential (pushpull) amplifier with adjustable gain which is capable of driving a 300 w load to + 12 dbm when v ext is 5 v. the po+ and po outputs are intended to drive loads differentially and not to v ss or v ag . the po+ and po power amplifiers may be powered down indepen- dently of the rest of the chip by connecting the pi pin to v dd or in br2 (b5). the other paired power driver outputs are the axo+ and axo auxiliary outputs. these pushpull output amplifiers are intended to drive a ringer or loud speaker with imped- ance as low as 300 w to + 12 dbm when v ext is 5 v. the axo+ and axo outputs are intended to drive loads dif- ferentially and not to v ss or v ag . the axo+ and axo power amplifiers may be powered down independently of the rest of the chip via the scp port in br2 (b6). sidetone the sidetone function of this device allows a controlled amount of the output from the transmit filter to be summed with the output of the dac at the input to the receive low pass filter. the sidetone component has gains of 8.5 db, 10.5 db, 12.0 db, 13.5 db, 15.0 db, 18.0 db, 21.5 db, and 70 db. the sidetone function is controlled by the scp port in br1 (b6:b4). universal tone generator the universal dual tone generator function supports both the transmit and the receive sides of this device. when the tone generator is being used, the decoder function of the dsp circuit is disabled. the output of the tone generator is made available to the input of the receive digital gain function for use at the receive analog outputs. in handset applica- tions, this could be used for generating dtmf, distinctive ringing or call progress feedback signals. in telephone line interface applications, this tone generator could be used for signaling on the line. the tone generator output is also available for the input to the encoder function of the dsp machine for outputting at the dt pin. this function is useful in
MC14LC5540 motorola 13 handset applications for nonnetwork signaling such as in- formation services, answering machine control, etc. at the network interface side of a cordless telephone application, this function could be used for dialing feedback or call prog- ress to the handset. the tone generator function is controlled by the scp port in br4, br5, and br7. the tone generator does not work when the device is operated in 64 kbps mode, except when analog loopback is enabled at br0 (b5). powerdown and reset there are two methods of putting all of this device into a low power consumption mode that makes the device non- functional and consumes virtually no power. pdi /reset is the powerdown input and reset pin which, when taken low, powers down the device. another way to power the device down is by the scp port at br0. br0 allows the analog sec- tion of this device to be powered down individually and/or the digital section of this device to be powered down individually. when the chip is powered down, the v ag , tg, ro, po+, po, axo+, axo, dt and scp tx outputs are high imped- ance. to return the chip to the powerup state, pdi /reset must be high and the spc clock and the fst or the fsr frame sync pulses must be present. the adpcm algorithm is reset to the ccitt initial state following the reset transition from low to high logic states. the dt output will remain in a highimpedance state for at least two fst pulses after pow- erup. this device is functional after being reset for fulldu- plex voice coding with the charge pump active. signal processing clock (spc) this is the clock that sequences the dsp circuit. this clock may be asynchronous to all other functions of this device. clock frequencies of 20.48 mhz to 24.32 mhz are recom- mended. this clock is also used to drive a digitally phase locked prescaler that is referenced to fst (8 khz) and automatically determines the proper divide ratio to use for achieving the required 256 khz internal sequencing clock for all analog signal processing, including analogtodigital conversion, digitaltoanalog conversion, transmit filtering, receive filtering and analog gain functions of this device, and the charge pump. the spc clock should be a multiple of 256 khz. the analog sequencing function of the spc clock may be eliminated by reprogramming the device to use the bclkr pin as the direct input for the required 256 khz analog se- quencing clock. the 256 khz clock applied at bclkr must be an integer 32 times the fst 8 khz clock and be approxi- mately rising edge aligned with the fst rising edge. this mode requires that the transmit and receive adpcm trans- fers be controlled by the bclkt pin. this is reprogrammed via the scp port in br0 (b7). digital i/o the MC14LC5540 is programmable for mulaw or a law. the timing for the pcm data transfer is independent of the companding scheme selected. table 1 shows the 8bit data word format for positive and negative zero and full scale for both 64 kbps companding schemes (see figures 1 through 5 for a summary and comparison of the five pcm data interface modes of this device). long frame sync long frame sync is the industry name for one type of clocking format which controls the transfer of the adpcm or pcm data words (see figures 1 through 4). the aframe synco or aenableo is used for two specific synchronizing func- tions. the first is to synchronize the pcm data word transfer, and the second is to control the internal analogtodigital and digitaltoanalog conversions. the term asynco refers to the function of synchronizing the pcm data word onto or off of the multiplexed serial pcm data bus, also known as a pcm highway. the term alongo comes from the duration of the frame sync measured in pcm data clock cycles. long frame sync timing occurs when the frame sync is used di- rectly as the pcm data output driver enable. this results in the pcm output going low impedance with the rising edge of the transmit frame sync, and remaining low impedance for the duration of the transmit frame sync. the implementation of long frame sync for this device has maintained industry compatibility and been optimized for external clocking simplicity. the pcm data output goes low impedance with the rising edge of the fst pin but the msb of the data is clocked out due to the logical and of the transmit frame sync (fst pin) with the transmit data clock (bclkt pin). this allows either the rising edge of the fst enable or the rising edge of the bclkt data clock to be first. this im- plementation includes the pcm data output remaining low impedance until the middle of the lsb (seven and a half data clock cycles for 64 kbps pcm, three and a half data clock cycles for 32 kbps adpcm, etc.). this allows the frame sync to be approximately rising edge aligned with the initiation of the pcm data word transfer but the frame sync does not have a precise timing requirement for the end of the pcm data word transfer. this prevents bus contention between similar devices on a common bus. the device recognizes long frame sync clocking when the frame sync is held high for two consecutive falling edges of the transmit data clock. in the fullduplex speech mode, the dsp services one en- code interrupt and one decode interrupt per frame (125 m s). the encode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps adpcm or 64 kbps pcm) is determined by the length of the transmit output enable at the fst pin. the length of the fst enable measured in transmit data clock (bclkt) cycles tells the device which encoding rate to use. this enable length in- formation is used by the encoder each frame. the transmit adpcm word corresponding to this request will be computed during the next frame and be available a total of two frames after being requested. this transmit enable length informa- tion can be delayed by the device an additional four frames corresponding to a total of six frames. this six frames of delay allows the device to be clocked with the same clocks for both transmit (encode) and receive (decode), and to be frame aligned for applications that require every sixth frame signaling. it is important to note that the enable length in- formation is delayed and not the actual adpcm (pcm) sam- ple word. the amount of delay for the fst enable length is controlled by the scp port at br7 (b5). the digital data out- put circuitry counts bclkt cycles to keep the data output (dt pin) low impedance for the duration of the adpcm data word (2, 3, 4, or 8 bclkt cycles) minus one half of a bclkt cycle.
MC14LC5540 motorola 14 table 1. pcm full scale and zero words ll mulaw alaw level sign bit chord bits step bits sign bit chord bits step bits + full scale 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 zero 0 111 1111 0 101 0101 full scale 0 000 0000 0 010 1010 the length of the fst enable tells the dsp what encoding algorithm to use. the transmit logic decides on each frame sync whether it should interpret the next frame sync pulse as a long or a short frame sync. the device is designed to prevent pcm bus contention by not allowing the pcm data output to go low impedance for at least two frame sync cycles after power is applied or when coming out of the powerdown mode. the receive side of the device is designed to accept the same frame sync and data clock as the transmit side and to be able to latch its own transmit pcm data word. thus the pcm digital switch only needs to be able to generate one type of frame sync for use by both transmit or receive sec- tions of the device. the logical and of the receive frame sync with the receive data clock tells the device to start latching the serial word into the receive data input on the falling edges of the receive data clock. the internal receive logic counts the receive data clock falling edges while the fsr enable is high and trans- fers the enable length and the pcm data word into internal registers for access by the dsp machine which also sets the dsp's decoder interrupt. the receive digital section of this device accepts serial adpcm (pcm) words at the dr pin under the control of the bclkr and fsr pins. the fsr enable duration measured in bclkr cycles, tells the device which decode algorithm (i.e., 16 kbps, 24 kbps, or 32 kbps adpcm, or 64 kbps pcm) the dsp machine should use for the word that is being re- ceived at the dr pin. this algorithm may be changed on a frame by frame basis. when the device is programmed to be in the pcm codec mode by br0 (4:3), the device will output and input the com- plete 8bit pcm words using the long frame sync clocking format as though the fst and fsr pulses were held high for 8 data clock cycles. the dsp machine receives an interrupt when an adpcm word has been received and is waiting to be decoded into a pcm word. the dsp machine performs a decode and an en- code every frame when the device is operating in its full duplex conversation mode. the dsp machine decodes the adpcm word according to ccitt g.726 for 32 kbps, 24 kbps, and 16 kbps. short frame sync short frame sync is the industry name for this type of clocking format which controls the transfer of the adpcm data words (see figure 5). this device uses short frame sync timing for 32 kbps adpcm only. the aframe synco or aenableo is used for two specific synchronizing functions. the first is to synchronize the adpcm data word transfer, and the second is to control the internal analog to digital and digital to analog conversions. the term asynco refers to the function of synchronizing the adpcm data word onto or off of the multiplexed serial adpcm data bus, also known as a pcm highway. the term ashorto comes from the duration of the frame sync measured in pcm data clock cycles. short frame sync timing occurs when the frame sync is used as a apresynchronizationo pulse that is used to tell the internal logic to clock out the adpcm data word under complete con- trol of the data clock. the short frame sync is held high for one falling data clock edge. the device outputs the adpcm data word beginning with the following rising edge of the data clock. this results in the adpcm output going low imped- ance with the rising edge of the transmit data clock, and re- maining low impedance until the middle of the lsb (three and a half pcm data clock cycles). the device recognizes short frame sync clocking when the frame sync is held high for one and only one falling edge of the transmit data clock. the transmit logic decides on each frame sync whether it should interpret the next frame sync pulse as a long or a short frame sync. it is not recom- mended to switch between long frame sync and short frame sync clocking without going through a powerdown cycle due to bus contention problems. the device is de- signed to prevent pcm bus contention by not allowing the adpcm data output to go low impedance for at least two frame sync cycles after power is applied or when coming out of a powered down mode. the receive side of the device is designed to accept the same frame sync and data clock as the transmit side and to be able to latch its own transmit adpcm data word. thus the pcm digital switch only needs to be able to generate one type of frame sync for use by both transmit or receive sec- tions of the device. the falling edge of the receive data clock (bclkr) latch- ing a high logic level at the receive frame sync (fsr) input tells the device to start latching the 4bit adpcm serial word into the receive data input on the following four falling edges of the receive data clock. the internal receive logic counts the receive data clock cycles and transfers the adpcm data word to a register for access by the dsp. when the device is programmed to be in the pcm codec mode by br0 (4:3), the device will output the complete 8bit pcm word using the short frame sync clocking format. the 8bit pcm word will be clocked out (or in) the same way that the 4bit adpcm word would be, except that the fourth bit will be valid for the full bclkt period and the eighth bit will be valid for only one half of the bclkt period.
MC14LC5540 motorola 15 serial control port register map the scp register map consists of 16 byte registers. regis- ters br0 br5 and br7 br10 provide external control of and status of the part. register br15 holds the value of the mask number for the particular MC14LC5540. br6 and br11 br14 are not defined and as such are presently re- served. table 2. byte register map byte b7 b6 b5 b4 b3 b2 b1 b0 br0 ext 256 khz clk mu/alaw select analog loopback i/o mode (1) i/o mode (0) charge pump disable analog power down digital power down br1 reserved sidetone gain (2) sidetone gain (1) sidetone gain (0) transmit mute transmit gain (2) transmit gain (1) transmit gain (0) br2 ro reference select axo enable po disable receive filter disable ro mute analog receive gain (2) analog receive gain (1) analog receive gain (0) br3 digital rx gain enable digital rx gain (6) digital rx gain (5) digital rx gain (4) digital rx gain (3) digital rx gain (2) digital rx gain (1) digital rx gain (0) br4 n.b. time / tone param. (7) n.b. time / tone param. (6) n.b. time / tone param. (5) n.b. time / tone param. (4) n.b.time / tone param. (3) n.b. time / tone param. (2) n.b. time / tone param. (1) n.b. time / tone param. (0) br5 n.b. threshold (7) / address param. (1) n.b. threshold (6) / address param. (0) n.b. threshold (5) / don't care n.b. threshold (4) / don't care n.b. threshold (3) / tone param. (11) n.b. threshold (2) / tone param. (10) n.b. threshold (1) / tone param. (9) n.b. threshold (0) / tone param. (8) br6 reserved reserved reserved reserved reserved reserved reserved reserved br7 tone param. status n.b. detect enable 2/6 delay g.726/ motorola 16 kbps tone enable reserved tone 1 enable tone 2 enable br8 software encoder reset software decoder reset linear codec mode highpass disable reserved reserved reserved reserved br9 encoder pcm (7) encoder pcm (6) encoder pcm (5) encoder pcm (4) encoder pcm (3) encoder pcm (2) encoder pcm (1) encoder pcm (0) br10 d/a pcm (7) d/a pcm (6) d/a pcm (5) d/a pcm (4) d/a pcm (3) d/a pcm (2) d/a pcm (1) d/a pcm (0) br11 reserved reserved reserved reserved reserved reserved reserved reserved br12 reserved reserved reserved reserved reserved reserved reserved reserved br13 reserved reserved reserved reserved reserved reserved reserved reserved br14 reserved reserved reserved reserved reserved reserved reserved reserved br15 reserved reserved reserved reserved mask (3) mask (2) mask (1) mask (0) note: asettingo a bit corresponds to writing a 1 to the register and aclearingo a bit corresponds to writing a 0 to the register.
MC14LC5540 motorola 16 application circuits 20 k w to microcontroller serial peripheral interface port and reset circuit 8 khz 2.048 mhz 20.736 mhz adpcm out adpcm in mic 0.1 m f 3 k w 150 w 0.1 m f receiver ringer 20 k w 20 k w + 2.7 v 1 k w 1 k w 1.0 m f 1.0 m f 1 k w 1 k w + 2.7 v c1 + c1 spc scp rx scpclk scp tx bclkt dt fst bclkr dr fsr v dd v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdi /reset axo + axo scpen pi po po + tg ti ti + ro v ag v dsp v ext 14 13 12 11 10 8 7 6 5 4 3 2 1 ? 9 MC14LC5540 0.1 m f 150 w 0.1 m f 1.0 m f 68 m f figure 11. MC14LC5540 handset application
MC14LC5540 motorola 17 nc nc r0 = 600 w 0.1 m f ring tip n = 1 n = 0.5 10 k w +5 v nc nc 20 k w to microcontroller serial peripheral interface port and reset circuit 8 khz 2.048 mhz 20.48 mhz adpcm out adpcm in 3 k w 10 k w +5 v c1 + c1 spc scp rx scpclk scp tx bclkt dt fst bclkr dr fsr v dd v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdi /reset axo + axo scpen pi po po + tg ti ti + ro v ag v dsp v ext 14 13 12 11 10 8 7 6 5 4 3 2 1 ? 9 MC14LC5540 0.1 m f 0.1 m f 0.1 m f 150 w figure 12. MC14LC5540 stepup 1:0.5 transformer application 0.1 m f ring tip n = 1 n = 1 10 k w +5 v nc nc 20 k w to microcontroller serial peripheral interface port and reset circuit 8 khz 2.048 mhz 20.736 mhz adpcm out adpcm in 20 k w 150 w speaker 10 k w +5 v c1 + c1 spc scp rx scpclk scp tx bclkt dt fst bclkr dr fsr v dd v ss 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pdi /reset axo + axo scpen pi po po + tg ti ti + ro v ag v dsp v ext 14 13 12 11 10 8 7 6 5 4 3 2 1 ? 9 MC14LC5540 0.1 m f 600 w 0.1 m f 0.1 m f ro = 600 w figure 13. MC14LC5540 1:1 transformer application
MC14LC5540 motorola 18 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. atypicalo parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. mfax is a trademark of motorola, inc. how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : nippon motorola ltd.: spd, strategic planning office, 4321, p.o. box 5405, denver, colorado 80217. 3036752140 or 18004412447 nishigotanda, shinagawaku, tokyo 141, japan. 81354878488 mfax ? : rmfax0@email.sps.mot.com touchtone 6 022446609 asia / pacific : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, us & canada only 18007741848 51 ting kok road, tai po, n.t., hong kong. 85226629298 internet : http://motorola.com/sps MC14LC5540ts/d ?

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